With advancements in technology, there is a constant need for increased computer processing speed and faster data transmission. Advanced design techniques for integrated circuits have attempted to address this need via the use of numerous different methods. One such method utilizes higher frequencies for data transmission. With the use of higher frequencies, the design of integrated circuits has moved from conventional clocking techniques to a newer scheme referred to as source synchronous data transfer.
Source synchronous data transfer transmits clock signals and bits of data via an integrated circuit memory and/or processor bus lines. Since the clock signal and data are linked during transmission between integrated circuits, any jitter, signal reflection, or other interference will affect both the clock signal and the data signal as a single entity, thereby ensuring that data is not lost between clock cycles. Therefore, newer generations of microprocessors utilize source synchronous data transfer techniques to increase processing and eliminate data transfer errors.
While source synchronous data transfer ensures that a data and a clock signal are transmitted simultaneously, transmission after reaching a destination integrated circuit (IC) is not controlled. Specifically, there is a difference between the arrival time of the clock signal and the arrival time for a data signal at an input register of a pad, or contact, located on the integrated circuit. The main cause of this difference is two-fold. First, there is a large propagation delay encountered between the input of a clock pad, where the clock signal is received, and a register intended to receive the clock signal. Second, there is also a delay encountered between the input of a data pad, where the data is received, and the register intended to receive the data. Unfortunately, the clock delay and data delay typically are not of the same in duration, thereby contributing to a lack of control of clock signal and data signal arrival times at the receiving register. It should be noted that, while synchronous data transfer transmits a clock signal and a data signal simultaneously, the clock signal and data signal do not arrive at the destination IC simultaneously.
It is well known in the art that it is not desirable for data to change during receipt by the receiving register. Likewise, it is also known that it is not desirable for a new clock signal to be received while a register is receiving data. Therefore, it is necessary to address these timing requirements.
While attempts may be made to compensate for these delays by skewing setup and hold times of the receiving register to reflect the delays, the uncertainty in the propagation of the clock signal and data signal associated with the register makes this method of compensation unsuccessful. Presently, standard cell delay elements are utilized in an attempt to match the delays of the clock signal and the data signal. Examples of these cell delay elements include, but are not limited to, two inverters in series following two weakened inverters, which are, in turn, followed by a large inverter. In addition, the clock path comprises a series of clock drivers, which are in series with stepped up symmetric buffers.
While adding the delay elements improves the setup and hold performance over the undelayed case, it still does not account for variations due to process, voltage and temperature (PVT) as well as unbalanced loading. In fact, architectural differences of the delay buffers causes substantial differences in their response to variations in PVT. This response difference leads to significant uncertainty in data and clock signal arrival times relative to each other, which can lead to larger setup and hold times for the receiving register, thereby resulting in slower data transmission.